Dual purpose serializer/de-serializer for point-to-point and point-to-multipoint communication

ABSTRACT

A dual purpose serializer/de-serializer (SerDes) for point-to-point and point-to-multipoint communication. A configurable SerDes can be designed to operate in one of a plurality of operating modes. Selection between the plurality of operating modes can be based on information received via a management interface. In one example, the various operating modes can be defined with different locking times and jitter characteristics.

BACKGROUND

1. Field of the Invention

The present invention relates generally to a serializer/de-serializer(SerDes) and, more particularly, to a dual purpose SerDes forpoint-to-point and point-to-multipoint communication.

2. Introduction

A SerDes is an integrated circuit (IC or chip) transceiver that convertsparallel data to serial data and vice-versa. The transmitter section hasparallel data lines coming in and a serial output data stream. Thetransmitter section can also have a phase-locked loop (PLL) thatmultiplies the incoming parallel clock up to the serial frequency. Forexample, a SerDes in a gigabit Ethernet system would include 10 paralleldata lines that can be clocked at 125 Mhz, with the resulting serialoutput clocked at 1.25 Ghz. The gigabit Ethernet SerDes would commonlyuse an 8B/10B coding scheme that maps 8-bit symbols to 10-bit symbols toachieve DC-balance on the line. As would be appreciated, the receiversection is the reverse of the transmitter section and would have aserial data stream coming in with parallel data lines coming out.

FIG. 1A illustrates the implementation of a SerDes component within agigabit Ethernet physical layer device (PHY). As illustrated, thegigabit Ethernet PHY includes a physical coding sublayer (PCS), aphysical medium attachment (PMA), and physical media dependent (PMD).The PCS is generally responsible for encoding/decoding gigabit mediaindependent interface (GMII) octets to/from ten-bit code-groups (8B/10B)for communication with the underlying PMA. Similarly, FIG. 1Billustrates the implementation of a SerDes component within a 10G PHY.As illustrated, the 10G Ethernet PHY's PCS is generally responsible forencoding/decoding 10 gigabit media independent interface (XGMII) 64-bitdata to/from 66-bit code-groups (64B/66B) for communication with theunderlying PMA.

In general, the PMA abstracts the PCS from the physical medium.Accordingly, the PCS can be unaware of whether the medium is copper orfiber. The primary functions of the PMA include mapping of transmit andreceive code-groups between the PCS and PMA,serialization/de-serialization of code-groups for transmission/receptionon the underlying serial PMD, recovery of clock from the coded data(e.g., 8B/10B, 64B/66B, etc.) supplied by the PMD, and mapping oftransmit and receive bits between the PMA and PMD.

The PMD is generally responsible for generating electrical or opticalsignals depending on the nature of the physical medium connected. PMDsignals are sent to the medium dependent interface (MDI), which is theactual medium connected, including connectors, for the various mediasupported.

As noted above, the PMA is responsible for the recovery of the receivedclock, which is used by the PCS to sample the data presented to it bythe PMA. Conventional clock recovery mechanisms use delay locked loops(DLLs) or phase locked loops (PLLs) that align a local clock's phase tothe phase of the recovered clock.

For point-to-point systems, the locking to an incoming embedded clock isa one-time event prior to the communication of data across the link. Forthis reason, the process of locking to an incoming embedded clock neednot be bounded by a particular locking time requirement. As would beappreciated, the relaxed timing requirement for locking to an incomingembedded clock can relax the design requirements of the SerDes.

In a point-to-multipoint system such as an Ethernet passive opticalnetwork (EPON), a single optical line terminal (OLT) at a head end canbe designed to communicate with a plurality of optical network units(ONTs) at various end nodes. This arrangement leverages a shared fiberoptic plant by multiple networking nodes. Typically, the OLT broadcastsits transmissions in the downstream direction to all the ONTs. Each ofthe ONTs, on the other hand, transmit in the upstream direction to theOLT. It should be noted that the OLT and ONTs need not transmit at thesame signaling rate or bandwidth. It should also be noted that the ONTscan be designed to share bandwidth or use a different wavelength in theupstream direction to eliminate overlap.

In receiving a plurality of individual communications from the variousconnected ONTs, the SerDes in the OLT is required to acquire phase andfrequency for each of the individual ONT communications. The locking toan incoming embedded clock is therefore not a one-time event. With astricter timing requirement to achieve a lock, the SerDes in the OLTfaces tighter design constraints.

In the SerDes market, point-to-point and point-to-multipoint solutionswill continue to exist as the markets expand. What is needed thereforeis a SerDes design that can leverage increased volumes while meeting theneeds of various point-to-point and point-to-multipoint applications.

SUMMARY

A dual purpose serializer/de-serializer for point-to-point andpoint-to-multipoint communication, substantially as shown in and/ordescribed in connection with at least one of the figures, as set forthmore completely in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to describe the manner in which the above-recited and otheradvantages and features of the invention can be obtained, a moreparticular description of the invention briefly described above will berendered by reference to specific embodiments thereof which areillustrated in the appended drawings. Understanding that these drawingsdepict only typical embodiments of the invention and are not thereforeto be considered limiting of its scope, the invention will be describedand explained with additional specificity and detail through the use ofthe accompanying drawings in which:

FIGS. 1A and 1B illustrate implementations of a SerDes component withingigabit and 10G Ethernet physical layer devices.

FIG. 2 illustrates an example of a point-to-multipoint communicationnetwork.

FIGS. 3A and 3B illustrate the communication between a single head endOLT and a plurality of end node ONTs.

FIG. 4 illustrates an example embodiment of the SerDes functionality ina PMA.

FIG. 5 illustrates a PHY that can be configured for use in multipleoperation modes.

FIG. 6 illustrates a flowchart of a process for configuring a SerDescomponent for use in one of multiple modes.

DETAILED DESCRIPTION

Various embodiments of the invention are discussed in detail below.While specific implementations are discussed, it should be understoodthat this is done for illustration purposes only. A person skilled inthe relevant art will recognize that other components and configurationsmay be used without parting from the spirit and scope of the invention.

A SerDes enables a quick and reliable transfer of data from one physicallocation to another. Here, data that exists in a parallel bus form isserialized to a single high-speed signal. In addition to the use of aSerDes in point-to-point systems, SerDes have also been incorporatedinto point-to-multipoint solutions.

FIG. 2 illustrates an example of a point-to-multipoint communicationnetwork. As illustrated, the point-to-multipoint network includes asingle OLT 210 that communicates to a plurality of ONTs 230-n via a PON.The illustrated PON includes splitter(s) 220, which enable a singlefeeder cable to be split into multiple drop cables for the individualONTs 230-n. In one embodiment, a single splitter (e.g., 1:16) is used.In another embodiment, two stages of splitting can be used. For example,a single 1:2 splitter can be combined with two 1:8 splitters toaccommodate 16 separate drop cables.

The advantage of the PON is that it allows sharing of the fiber opticplant by multiple network nodes. FIGS. 3A and 3B illustrate an exampleof the downstream and upstream communication between a single head endOLT and a plurality of end node ONTs in an Ethernet PON (EPON). In thedownstream direction illustrated in FIG. 3A, OLT 310 transmits packets1, 2, 3 for each of the respective connected ONTs 331, 332, 333. Asillustrated, each of ONTs 331, 332, 333 receive the stream of packets,wherein each of ONTs 331, 332, 333 are responsible for extracting theparticular packet that is destined for that location.

In the upstream direction illustrated in FIG. 3B, each of ONTs 331, 332,33 transmit their own packets back to OLT 310. In this upstreamcommunication process, ONTs 331, 332, 333 are designed to transmit in away to avoid collisions between the packets. In one embodiment, the PONuses a time division multiple access (TDMA) communication protocol. Inthis way, the individual packet communications from ONTs 331, 332, 333would be designed to fit into assigned time slots for transmission toOLT 310.

As has been described, the downstream transmission by OLT 310 iscontinuous as each ONT receives the same stream of packets. Thisdirection of communication would be similar to a point-to-point systemin that the SerDes in ONTs 331, 332, 333 can perform a one-time lock tothe incoming embedded clock.

In the upstream direction, on the other hand, the SerDes in OLT 310receives a plurality of individual communication streams from ONTs 331,332, 333 in the upstream direction. This burst-mode communication in thePON places a significant burden on the SerDes in OLT 310. Instead of aone-time lock to an incoming embedded clock, the SerDes in OLT 310 mustrepeatedly lock to the incoming data streams from ONTs 331, 332, 333.This results since the clocks used by each of ONTs 331, 332, 333 canvary to different degrees in frequency and phase.

As noted, the SerDes functionality is typically implemented in the PMA.FIG. 4 illustrates an example embodiment of the SerDes functionality ina PMA. As illustrated, the PMA includes parallel-in-serial-out (PISO)block 410 that takes the TX code group output from the PCS and generatesa serial output for the PMD. The operation of PISO 410 is based on aclock signal generated by clock multiplier unit (CMU) 420, whichmultiplies the incoming parallel PMA TX clock. In one embodiment, PISO410 has a single shift register that receives the parallel data once perparallel clock and shifts it out at the higher serial clock rate.

For a gigabit Ethernet system, the TX code group would be generated byan 8B/10B encoder, with PISO 410 operating in accordance with a 125 Mhzclock multiplied by 10 to produce a 1.25 Ghz clock. For a 10G Ethernetsystem, the TX code group would be generated by a 64B/66B encoder, withPISO 410 operating in accordance with a 644.5 Mhz clock multiplied by 16to produce a 10.3125 Ghz clock.

On the receive side, the PMA includes serial-in-parallel-out (SIPO)block 440 that takes the serial input from the PMD and generates the RXcode group for the PMA. The RX code group is processed by the PCS inaccordance with an embedded clock in the received signal. This recoveredclock signal is generated by clock recovery unit (CRU) 430, whichdivides the incoming clock down to the parallel rate for output to thePCS. In one embodiment, the operation of CRU 430 is based on a delaylocked loop (DLL) or a phase locked loop (PLL). As would be appreciated,the specific location of the DLL or PLL within the PHY would beimplementation dependent.

With burst-mode communication, the SerDes would need to lock onto eachindividual communication stream from the various ONTs. This lockingprocess would be governed by a much stricter timing requirement ascompared to standard point-to-point communication. For example, while apoint-to-point system can operate satisfactorily with a locking time ofapproximately 1000 bit times, the operation in a burst-modecommunication can require a stricter threshold that may be at least oneorder of magnitude lower.

One technique that can be used to decrease the locking time is toprevent the receive DLL/PLL from floating. In effect, a floating PLLwould require locking from a cold start. To ease this condition, theclock recovery can be tied to the transmit clock to prevent straying.FIG. 4 illustrates an example of this technique where CRU 430 alsoreceives the transmit clock via signal path 450. In burst-modeoperation, CRU 430 can then use the transmit clock in the transitionbetween different streams to assure that the locking time is minimized.

In general, the reduction of the locking time comes at a cost. Forexample, efforts to produce a shorter locking process produce worsejitter results. A tradeoff between lock timing and jitter thereforeresults. In addition, the need to improve the locking time can lead tobroader re-architecture efforts such as the use of digital signalprocessing (DSP) as compared to CMOS or Bi-CMOS technology. Herein liesanother tradeoff as DSP solutions typically required greater amounts ofpower.

In accordance with the present invention, it is recognized that theoperation of a SerDes in point-to-point and point-to-multipoint modesleads to significant design tradeoffs on varying levels. These designtradeoffs lead to differentiated SerDes designs that are necessarilytargeted at a particular mode of operation. In the manufacturingcontext, this leads to significant cost inefficiencies as the productionof multiple designs leads to an inability to benefit from largeeconomies of scale.

It is therefore a feature of the present invention that a SerDes designis provided that is operational in multiple modes. In one embodiment,the SerDes design is functional in both point-to-point andpoint-to-multipoint modes of operation. To illustrate the principles ofthe present invention, reference is now made to FIG. 5, whichillustrates an example gigabit Ethernet SerDes transceiver that can beconfigured for use in multiple operational modes.

As illustrated, SerDes transceiver 500 includes transmitter section 510and receiver section 520. Transmitter section 510 includes transmitter511, PISO 512, encoder 513 (e.g., 8B/10B, 64B/66B, etc.), and transmitFIFO 514. Receiver section 520 includes receiver 521, SIPO 522, clockrecovery 523, decoder 524 (e.g., 8B/10B, 64B/66B, etc.), and alignmentFIFO 525.

As FIG. 5 further illustrates, SerDes transceiver 500 also includesconfiguration registers 530. Configuration registers 530 represents acommon functional block that enables storage of configuration parametersthat can be used to configure one or more of transmit section 510 andreceiver section 520. As would be appreciated, transmitter section 510and receiver section 520 can also share common logic components such asa timing block.

In one embodiment, the configuration parameters in configurationregisters 530 can be programmed through a management interface (notshown). For example, the management interface can define the operationalcharacteristics of a DLL/PLL. In one scenario, the operationalcharacteristics can define the relative tradeoff between lock timing andjitter. In another scenario, the operational characteristics can definethe relative power consumption. As such, the management interface can beused to configure the operational mode of the SerDes to enable it, forexample, to operate in either a point-to-point or point-to-multipointenvironment.

In one embodiment, SerDes transceiver 500 can also be configured withone or more pins that can dictate SerDes receiver operation depending ona mode of operation. For example, a pin can be used to control the timesthat the receiver is locked to the transmit clock and the times that thereceiver is locked to the embedded clock in the received signal. Thecontrol using this pin would be useful when operating in apoint-to-multipoint mode to prevent the receiver from floating duringthe transition time between received streams.

To illustrate flexibility of operation in the SerDes of the presentinvention, reference is now made to the flowchart of FIG. 6. Asillustrated, the process begins at step 602 where one or more parametersreceived via a management interface are stored in the configurationregister(s). In one example, these configuration registers are loadedupon an identification of the particular environment in which the SerDeswill be used. For instance, if the SerDes is to be used in an OLT, thenit can be configured for point-to-point or point-to-multipoint use.Similar configurations can also be used for SerDes to be included in anONT. The key here is that a single SerDes design can be manufactured.This is in contrast to a situation where one SerDes design is forpoint-to-point use, while another SerDes design is forpoint-to-multipoint use. Manufacturing efficiencies can therefore beleveraged in the sales of SerDes components to customers.

After the configuration register(s) are set, at step 604, the SerDes canthen be configured for operation based on the contents of theconfiguration register(s). For example, the SerDes can be configuredupon powering to operate in accordance with one or more configurationparameters that are retrieved from the configuration register(s). Aswould be appreciated, the particular type and manner of configuration ofthe SerDes would be implementation dependent. The significance is theconfigurability of the SerDes itself.

Finally, at step 606, the embedded clock is recovered from the receivedsignal using the configured mode of operation. As noted, the clockrecovery process could be enabled by a DLL/PLL that has been configuredusing the configuration parameter(s). In another example, the clockrecovery process can be aided by one or more pins that dictateparticular signal routings within the SerDes. As noted above, a pin canbe used to dictate whether the SerDes is locked to the transmit clock,such as during a transition time between different communicationstreams.

As has been described, a SerDes mechanism has been provided that enablesa single SerDes design to be applied to various modes of operation.These various modes of operation can represent those modes that are ondifferent ends of a design tradeoff.

It should be noted that the principles of the present invention outlinedabove can be applied to various contexts. For example, the principles ofthe present invention can be used in SerDes of different standard ornon-standard network speeds (e.g., 1G, 2.5G, 10G, etc.), and variouspoint-to-point (e.g., Ethernet, non-Ethernet, etc.) andpoint-to-multipoint networks (e.g., PON, EPON, EPON, 10GEPON, etc.),

These and other aspects of the present invention will become apparent tothose skilled in the art by a review of the preceding detaileddescription. Although a number of salient features of the presentinvention have been described above, the invention is capable of otherembodiments and of being practiced and carried out in various ways thatwould be apparent to one of ordinary skill in the art after reading thedisclosed invention, therefore the above description should not beconsidered to be exclusive of these other embodiments. Also, it is to beunderstood that the phraseology and terminology employed herein are forthe purposes of description and should not be regarded as limiting.

1. A serializer/de-serializer, comprising: an operation mode managementinterface; and a clock recovery module that is configurable to operatein a first mode capable of locking onto an incoming embedded clockwithin a first locking time period, and in a second mode capable oflocking onto an incoming embedded clock within a second locking timeperiod shorter than said first locking time period, wherein aconfiguration of said clock recovery module is based on data received atsaid operation mode management interface.
 2. Theserializer/de-serializer of claim 1, further comprising configurableregisters that store parameters for one of said first mode and saidsecond mode.
 3. The serializer/de-serializer of claim 1, wherein saidclock recovery module includes a phase locked loop.
 4. Theserializer/de-serializer of claim 1, wherein said clock recovery moduleincludes a delay locked loop.
 5. The serializer/de-serializer of claim1, wherein said first locking time period is for use in a point-to-pointcommunication network.
 6. The serializer/de-serializer of claim 1,wherein said second locking time period is for use in apoint-to-multipoint communication network.
 7. Theserializer/de-serializer of claim 1, wherein said first mode has abetter jitter characteristic than said second mode.
 8. Aserializer/de-serializer, comprising: a clock recovery module that isconfigurable to operate in a first mode capable of locking onto anincoming embedded clock within a first locking time period, and in asecond mode capable of locking onto an incoming embedded clock within asecond locking time period shorter than said first locking time period,wherein a configuration of said clock recovery module is based on datareceived at an operation mode management interface.
 9. Theserializer/de-serializer of claim 8, further comprising configurableregisters that store parameters for one of said first mode and saidsecond mode.
 10. The serializer/de-serializer of claim 8, wherein saidclock recovery module includes a phase locked loop.
 11. Theserializer/de-serializer of claim 8, wherein said clock recovery moduleincludes a delay locked loop.
 12. The serializer/de-serializer of claim8, wherein said first locking time period is for use in a point-to-pointcommunication network.
 13. The serializer/de-serializer of claim 8,wherein said second locking time period is for use in apoint-to-multipoint communication network.
 14. Theserializer/de-serializer of claim 8, wherein said first mode has abetter jitter characteristic than said second mode.
 15. Aserializer/de-serializer method, comprising: storing a parameter in aconfigurable register of a serializer/de-serializer, said parameterbeing received by said serializer/de-serializer via an operation modemanagement interface; and configuring a clock recovery module of saidserializer/de-serializer to operate in one of a first operating mode anda second operating mode, said configuring being based on said parameterstored in said configurable register, wherein said first operating modeis capable of locking onto an incoming embedded clock within a firstlocking time period, and said second operating mode is capable oflocking onto an incoming embedded clock within a second locking timeperiod shorter than said first locking time period.
 16. The method ofclaim 15, wherein said configuring comprises configuring a phase lockedloop.
 17. The method of claim 15, wherein said configuring comprisesconfiguring a delay locked loop.